1. Field of the Invention
The present invention relates to a compound semiconductor device and a manufacturing method of the same, particularly, to a compound semiconductor device and a manufacturing method of the same which are capable of enhancing characteristics of field effect transistors and reducing defects in wire bonding.
2. Background Art
Mobile communication devices such as mobile telephones often use microwaves in a gigahertz range and frequently use switching devices to switch antennas or transmitting/receiving for switching those high frequency signals (see Japanese Patent Application Publication No. Hei 9-181642, for example). Such devices often use field effect transistors (hereinafter referred to as FETs) using gallium arsenide (GaAs) to deal with microwave signals. In this concern, development of monolithic microwave integrated circuits (MMICs) configured to integrate the above-mentioned switching circuits are now in progress.
FIG. 17 is a schematic circuit diagram showing a principle of a compound semiconductor switching circuit called SPDT (single pole double throw) which uses FETs.
Here, sources (or drains) of first and second field effect transistors FET1 and FET2 are connected to common input terminal IN, and gates of the field effect transistors FET1 and FET2 are connected to first and second control terminals Ctl-1 and Ctl-2 through resistors R1 and R2, respectively. Moreover, drains (or sources) of the FETs are connected to first and second output terminals OUT1 and OUT2, respectively. Signals applied to the first and second control terminals Ctl-1 and Ctl-2 are complementary signals, and the FET to which a H-level signal is applied is turned ON to transmit a high frequency signal entered to the input terminal IN to one of the output terminals. The resistors R1 and R2 are disposed in order to prevent leakage of high frequency signals through the gate electrodes with respect to direct current potential at the control terminals Ctl-1 and Ctl-2, which is a AC ground potential.
A GaAs substrate is semi-insulating. However, in the case of integrating a switching circuit on the GaAs substrate, if a pad electrode layer for wire bonding is provided directly on the substrate, an electric interaction will remain between adjacent electrodes. Such an aspect may cause a lot of problems such as occurrence of damages by electrostatic discharge due to low insulation strength or deterioration in isolation due to leakage of a high frequency signal. Accordingly, a nitride film has been provided below a wiring layer or below pad electrodes in a conventional manufacturing method.
However, the nitride film is hard and therefore causes cracks on pad portions by pressure at the time of bonding. To suppress such cracks, gold plating has been applied to bonding electrodes on the nitride film. However, a gold plating process causes increases in the number of processes and in costs. Therefore, a technique for avoiding provision of the nitride film below the pad electrodes has been developed.
An example of a method of manufacturing FETs, pads, and wirings collectively constituting the conventional compound semiconductor switching circuit shown in FIG. 17 will be described with reference to FIG. 18A to FIG. 19B.
Firstly, as shown in FIG. 18A, an entire surface of compound semiconductor substrate 51 made of GaAs or the like is covered with silicon nitride film 53 for through-ion implantation in a thickness from about 100 Å to 200 Å. Next, a photolithography process for selectively forming an opening on a resist layer (not shown) above a channel layer formation region is performed. Thereafter, ions of a p−-type impurity (24Mg+) are implanted and ions of an n-type impurity (29Si+) are implanted.
As a result, p−-type region 55 is formed on the undoped substrate 51 and n-type channel layer 52 is formed thereon.
Next, the resist layer used in the precedent step is removed and the entire surface of the resultant structure is covered with silicon nitride film 53 for cap annealing. New resist layer 58 is provided and a photolithography process is performed to selectively form openings in the resist layer 58 above respective formation regions for source region 56, drain region 57, gate wiring 62, and first pad electrode 91. Subsequently, ions i of an n-type impurity (29Si+) are implanted on the surface of the substrate in the respective formation regions for the source region 56, the drain region 57, the gate wiring 62, and the first pad electrode 91 while using this resist 58 as a mask. In this way, the n+-type source region 56 and drain region 57 are formed, and high concentration impurity region 60 for enhancing isolation is simultaneously formed on the surface of the substrate below the formation regions for the pad electrode 91 and the gate wiring 62. After removing the resist, activation annealing is performed to activate the n-type channel layer 52, the n+-type source region 56 and drain region 57, and the high concentration impurity region 60.
As shown in FIG. 18B, resist layer 63 is provided again and a photolithography process is performed to selectively form openings for formation regions for first source electrode 65 and first drain electrode 66. The silicon nitride film 53 above the formation regions for the first source electrode 65 and the first drain electrode 66 is removed by CF4 plasma, and subsequently, three layers of AuGe/Ni/Au collectively constituting ohmic metal layer 64 are sequentially evaporated by vacuum evaporation. Thereafter, the resist layer 63 is removed and the first source electrode 65 and the first drain electrode 66 are left on the source region 56 and the drain region 57 in contact by a lift-off method. Subsequently, ohmic junctions between the first source electrode 65 and the source region 56 and between the first drain electrode 66 and the drain region 57 are formed by an alloying heat treatment.
Next, as shown in FIG. 18C, a new resist layer (not shown) is provided and a photolithography process is performed to selectively form openings for respective formation regions for gate electrode 69, the first pad electrode 91, and the gate wiring 62. The silicon nitride film 53 exposed from the formation regions for the gate electrode 69, the first pad electrode 91, and the gate wiring 62 is subjected to dry etching, thereby exposing the channel layer 52 in the formation region for the gate electrode 69 and exposing the substrate 51 in the formation regions for the gate wiring 62 and the first pad electrode 91.
Thereafter, four layers of Pt/Ti/Pt/Au collectively constituting a gate metal layer as electrodes of a second metal layer are sequentially evaporated on the substrate 51 by vacuum evaporation. Then, the gate electrode 69, the first pad electrode 91, and the gate wiring 62 are formed by the lift-off method. Thereafter, a heat treatment for burying Pt is performed.
In this way, part of the gate electrode 69 is buried in the channel layer 52 while maintaining a Schottky junction with the substrate. By burying part of the gate electrode 69 in the channel layer 52, current density, channel resistance, and a high frequency distortion characteristic of a FET are substantially improved.
Then, as shown in FIG. 19A, passivation film 72 made of a silicon nitride film is formed on the surface of the substrate 51, and then a photolithography process and nitride film etching are performed. Accordingly, contact holes for the first source electrode 65, the first drain electrode 66, the gate electrode 69, and the first pad electrode 91 are formed on the passivation film 72.
After removing the resist, a new resist layer (not shown) is coated and a photolithography process is performed to selectively form openings in the resist above formation regions for second source electrode 75, second drain electrode 76, and second pad electrode 92. Subsequently, three layers of Ti/Pt/Au collectively constituting pad metal layer 74 as electrodes of a third metal layer are sequentially evaporated by vacuum evaporation and the lift-off method is performed thereon, thereby forming the second source electrode 75, the second drain electrode 76, and the second pad electrode 92 contacting the first source electrode 65, the first drain electrode 66, and the first pad electrode 91, respectively. Here, part of wiring portions are made by use of this pad metal layer 74, so that the pad metal layer 74 corresponding to the wiring portions are naturally left over.
Then, as shown in FIG. 19B, bonding wire 80 is bonded onto the second pad electrode 92. This technology is described for instance in Japanese Patent Application Publication No. 2003-007724.
As described above, the high concentration impurity regions 60 are provided below the pad electrode 91 and 92 and below the gate wiring 62 so as to protrude out of these regions. In this way, it is possible to suppress depletion layers extending from the pad electrodes 91 and 92 and the gate wiring 62 toward the substrate. Therefore, sufficient isolation can be ensured even when the pad electrodes 91 and 92 and the gate wiring 62 are provided directly on the GaAs substrate. Accordingly, it is possible to remove the nitride film which has been conventionally provided for the purpose of insulation.
When the nitride film is not required, it is not necessary to consider cracks of the nitride film under the pad electrodes 91 and 92 at the time of bonding of the bonding wire. Therefore, it is possible to omit the gold plating process which has been conventionally required. The gold plating process causes increases in the number of processes and in costs. That is, if it is possible to omit this process, such a technique can contribute largely to simplification of the manufacturing process and to cost reduction.
However, it is made clear that many problems occur at the time of bonding of the bonding wire when part of the gate electrode 69 was buried in the channel layer 52 to enhance characteristics of the FET as shown in FIG. 18C.
Part of the first pad electrode 91 made of gate metal layer 68 is also buried in the surface of the substrate in the step of the process to bury the gate electrode 69. That is, the problem is considered due to formation of a hard alloy layer as a result of a reaction of Pt of the lowermost layer of the first pad electrode 91 to Ga or As contained in the material for the substrate.
For this reason, problems such as degradation in bonding adhesion or gouges on the substrate occur and lead to reduction in yields or deterioration